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NCP1597B Product Preview 1 MHz, 2 A Synchronous Buck Regulator
The NCP1597B is a fixed 1 MHz, high-output-current, synchronous PWM converter that integrates a low-resistance, high-side P-channel MOSFET and a low-side N-channel MOSFET. The NCP1597B utilizes current mode control to provide fast transient response and excellent loop stability. It regulates input voltages from 4.0 V to 5.5 V down to an output voltage as low as 0.8 V and is able to supply up to 2 A. The NCP1597B has features including fixed internal switching frequency (FSW), and an internal soft-start to limit inrush current. Using the EN pin, shutdown supply current is reduced to 3 mA maximum. Other features include cycle-by-cycle current limiting; short-circuit protection, low dropout mode, power saving mode and thermal shutdown.
Features http://onsemi.com MARKING DIAGRAM
1597B ALYWG G
DFN10 CASE 485C
* Input Voltage Range: from 4.0 V to 5.5 V * Internal 140 mW High-Side Switching P-Channel MOSFET and * * * * * * * * * * * * * * * * * *
90 mW Low-Side N-Channel MOSFET Fixed 1 MHz Switching Frequency Cycle-by-Cycle Current Limiting Overtemperature Protection Internal Soft-Start Start-up with Pre-Biased Output Load Adjustable Output Voltage Down to 0.8 V Power Saving Mode During Light Load Low Dropout Mode Operation to Extend the Battery Life These are Pb-Free Devices DSP Power Hard Disk Drivers Computer Peripherals Home Audio Set-Top Boxes Networking Equipment LCD TV Wireless and DSL/Cable Modem USB Power Devices
1597B = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
EN 1 VCC 2 VCCP 3 AGND 4 FB 5 (Top View) 10 PGND 9 PGND 8 LX 7 LX 6 NC
ORDERING INFORMATION
Device NCP1597BMNTWG NCP1597BMNTXG Package DFN10 (Pb-Free) DFN10 (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel
Applications
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 2009
October, 2009 - Rev. P0
1
Publication Order Number: NCP1597B/D
NCP1597B
BLOCK DIAGRAM
NCP1597B VCCP VCC Power Reset UVLO THD Hiccup + CA -
EN
+
OSC
Soft-Start
PMOS M1 LX + + gm - - PWM + Control Logic LX
Vref FB
AGND PGND
Figure 1. Block Diagram PIN DESCRIPTIONS
Pin No 1 2 3 4 5 6 7, 8 9, 10 EP Symbol EN VCC VCCP AGND FB NC LX PGND PAD Description Logic input to enable the part. Logic high turns on the part and a logic low disables it. An internal pullup forces the part into an enable state when no external bias is present on the pin. Input supply pin for internal bias circuitry. A 0.1 mF ceramic bypass capacitor is preferred to connect to this pin. Power input for the power stage Analog ground pin. Connect to thermal pad. Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter's output voltage to this pin to set the converter's output voltage. No connection The drains of the internal MOSFETs. The output inductor should be connected to these pins. Power ground pins. Connect to thermal pad. Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the PCB for proper operation.
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NCP1597B
APPLICATION CIRCUIT
Vin 4.0 V - 5.5 V
2 VCC 3 VCCP 1 EN 6 NC 4 AGND
LX LX FB
8 7 5
Vout
PGND 10 PGND 9
NCP1597B
Figure 2. NCP1597B
ABSOLUTE MAXIMUM RATINGS
Rating Power Supply Pin (Pin 4, 5) to GND LX to GND All other pins Operating Temperature Range Junction Temperature Storage Temperature Range Pkg Power Dissipation (TA = +25C) TA TJ TS PD Symbol Vin Value -0.3 V (DC) to 7.0 V -1.0 V For T < 100 ns -0.6 V to Vin + 0.3 V, -1.0 V For T < 100 ns -0.3 V to 6.5 V, -1.0 V For T < 100 ns -40 to +85 -40 to +150 -55 to +150 68.5 C C C C/W Unit
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCP1597B
ELECTRICAL CHARACTERISTICS
(Vin = 4.0 V - 5.5 V, Vout = 1.2 V, TJ = +25C for typical value; -40C < TJ < 125C for min/max values unless noted otherwise) Parameter Vin Input Voltage Range VCC UVLO Threshold UVLO Hysteresis VCC Quiescent Current VCCP Quiescent Current Vin Shutdown Supply Current (Note 1) FEEDBACK VOLTAGE Reference Voltage Feedback Input Bias Current Feedback Voltage Line Regulation PWM Maximum Duty Cycle (regulating) LDO Mode Threshold Voltage (falling) LDO Mode Threshold Hysteresis (rising) Minimum Controllable ON Time (Note 1) PULSE-BY-PULSE CURRENT LIMIT Pulse-by-Pulse Current Limit OSCILLATOR Oscillator Frequency MOSFET High Side MOSFET ON Resistance High Side MOSFET Leakage (Note 1) Low Side MOSFET ON Resistance Low Side MOSFET Leakage (Note 1) ENABLE EN HI Threshold EN LO Threshold EN Hysteresis EN Pullup Current SOFT-START Soft-Start Ramp Time Hiccup Timer THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis 1. Guaranteed by design. Not production tested. 170 40 C C tSS FSW = 1 MHz 1.0 2.0 ms ms ENHI ENLO 300 1.4 3.0 1.4 0.4 V V mV mA RDS(on) HS RDS(on) LS IDS = 100 mA, VGS = 5 V VEN = 0 V, VSW = 0 V IDS = 100 mA, VGS = 5 V VEN = 0 V, VSW = 5 V 90 140 200 10 125 10 mW mA mW mA FSW 0.87 1.0 1.13 MHz ILIM 2.6 3.0 3.4 A 83 0.74 0.75 12 50 0.76 % V mV ns Vref IFB VFB = 0.8 V Vin = 4.0 V to 5.5 V 0.788 0.800 10 0.03 0.812 100 V nA %/V IinVCC IinVCCP IQSHDN Vin = 5.0 V, VFB = 1.5 V, (No Switching) Vin = 5.0 V,VFB = 1.5 V, (No Switching) EN = 0 V Symbol Vin Test Conditions Min 4.0 3.5 3.7 180 1.1 60 1.4 3.0 2.0 Typ Max 5.5 3.9 Unit V V mV mA mA mA
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NCP1597B
DETAILED DESCRIPTION
Overview
The NCP1597B is a synchronous PWM controller that incorporates all the control and protection circuitry necessary to satisfy a wide range of applications. The NCP1597B employs current mode control to provide fast transient response, simple compensation, and excellent stability. The features of the NCP1597B include a precision reference, fixed 1 MHz switching frequency, a transconductance error amplifier, an integrated high-side P-channel MOSFET and low-side N-Channel MOSFET, internal soft-start, and very low shutdown current. The protection features of the NCP1597B include internal soft-start, pulse-by-pulse current limit, and thermal shutdown.
Reference Voltage
drive signal to avoid shoot through. During the dead time, the body diode of the low side FET freewheels the current. The body diode has much higher voltage drop than that of the MOSFET, which reduces the efficiency significantly. The longer the body diode conducts, the lower the efficiency. In NCP1597B, the drivers and MOSFETs are integrated in a single chip. The parasitic inductance is minimized. Adaptive dead time control method is used in NCP1597B to prevent the shoot through from happening and minimizing the diode conduction loss at the same time.
Pulse Width Modulation
The NCP1597B incorporates an internal reference that allows output voltages as low as 0.8 V. The tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. The reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents.
Oscillator Frequency
A fixed precision oscillator is provided. The oscillator frequency range is 1 MHz with $13% variation.
Transconductance Error Amplifier
A high-speed PWM comparator, capable of pulse widths as low as 50 ns, is included in the NCP1597B. The inverting input of the comparator is connected to the output of the error amplifier. The non-inverting input is connected to the the current sense signal. At the beginning of each PWM cycle, the CLK signal sets the PWM flip-flop and the upper MOSFET is turned ON. When the current sense signal rises above the error amplifier's voltage then the comparator will reset the PWM flip-flop and the upper MOSFET will be turned OFF. When input and output voltage gets close to each other, the high side FET will be ON all the time (100% duty cycle) and the part operates in a low dropout mode.
Low Dropout Mode operation
The transconductance error amplifier's primary function is to regulate the converter's output voltage using a resistor divider connected from the converter's output to the FB pin of the controller, as shown in the applications Schematic. If a Fault occurs, the COMP pin is immediately pulled to GND and PWM switching is inhibited.
Internal Soft-Start
To limit the startup inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 V to its final value linearly. The internal soft start time is 1 ms typically.
Output MOSFETs
When the input voltage and output voltage come close to each other, the NCP1597B enters into LDO (low dropout) mode. The high side FET is turned on 100% for one or more cycles. With further decreasing of input voltage, the high side FET will be on completely. In this case, the converter offers a low voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range.
Power Save Mode
The NCP1597B includes low RDS(on), both high-side P-channel and low-side N-channel MOSFETs capable of delivering up to 2.0 A of current. When the controller is disabled or during a Fault condition, the controller's output stage is tri-stated by turning OFF both the upper and lower MOSFETs.
Adaptive Dead Time Gate Driver
If the load current decreases, the converter will enter power save mode operation automatically. During power save mode, the converter skips switching and operates with reduced frequency, which minimizes the quiescent current and maintain high efficiency.
Current Sense Amplifier
A high-bandwidth current sense amplifier monitors the current in the upper MOSFET. The current signal is required by the PWM comparator, the pulse-by-pulse current limiter.
In a synchronous buck converter, a certain dead time is required between the low side drive signal and high side
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NCP1597B
PROTECTIONS
Undervoltage Lockout (UVLO)
The under voltage lockout feature prevents the controller from switching when the input voltage is too low to power the internal power supplies and reference. Hysteresis must be incorporated in the UVLO comparator to prevent IxR drops in the wiring or PCB traces from causing ON/OFF cycling of the controller during heavy loading at power up or power down.
Overcurrent Protection (OCP)
limit circuit limits peak current to 3.0 A during overload and short circuit conditions.
Pre-Bias Startup
NCP1597B detects high side switch current and then compares to a voltage level representing the overcurrent threshold limit. If the current through high side FET exceeds the overcurrent threshold limit, overcurrent protection is triggered. The system ignores the overcurrent signal for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches. Then the high side MOSFET is turned-off for the rest of cycle after a propagation delay. This cycle-by-cycle current
In some applications the controller will be required to start switching when it's output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter's output capacitors may have residual charge on them or the converter's output may be held up by a low current standby power supply. NCP1597B supports pre-bias start up by holding Low side FETs off till soft start ramp reaches the FB Pin voltage.
Thermal Shutdown
The NCP1597B protects itself from over heating with an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold both the upper and lower MOSFETs will be shut OFF.
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NCP1597B
APPLICATION INFORMATION
Programming the Output Voltage
The output voltage is set using a resistive voltage divider from the output voltage to FB pin (see Figure 3). So the output voltage is calculated according to Eq.1.
V out + V FB @
Vout
C OUT(min) +
I ripple 8 @ f @ V ripple
(eq. 3)
R1 ) R2 R2
(eq. 1)
Where Vripple is the allowed output voltage ripple. The required ESR for this amount of ripple can be calculated by equation 5.
ESR + V ripple I ripple
(eq. 4)
R1
FB R2
Based on Equation 2 to choose capacitor and check its ESR according to Equation 3. If ESR exceeds the value from Eq.4, multiple capacitors should be used in parallel. Ceramic capacitor can be used in most of the applications. In addition, both surface mount tantalum and through-hole aluminum electrolytic capacitors can be used as well.
Maximum Output Capacitor
Figure 3. Output divider Inductor Selection
NCP1597B family has internal 1 ms fixed soft-start and overcurrent limit. It limits the maximum allowed output capacitor to startup successfully. The maximum allowed output capacitor can be determined by the equation:
C out(max) + I lim(min) * I load(max) * V out T SS(min)
Di p-p 2
The inductor is the key component in the switching regulator. The selection of inductor involves trade-offs among size, cost and efficiency. The inductor value is selected according to the equation 2.
L+ V out f @ I ripple @ 1* V out V in(max)
(eq. 2)
(eq. 5)
Where Vout - the output voltage; f - switching frequency, 1.0 MHz; Iripple - Ripple current, usually it's 20% - 30% of output current; Vin(max) - maximum input voltage. Choose a standard value close to the calculated value to maintain a maximum ripple current within 30% of the maximum load current. If the ripple current exceeds this 30% limit, the next larger value should be selected. The inductor's RMS current rating must be greater than the maximum load current and its saturation current should be about 30% higher. For robust operation in fault conditions (start-up or short circuit), the saturation current should be high enough. To keep the efficiency high, the series resistance (DCR) should be less than 0.1 W, and the core material should be intended for high frequency applications.
Output Capacitor Selection
Where TSS(min) is the minimum soft-start period (1ms); DiPP is the current ripple. This is assuming that a constant load is connected. For example, with 3.3 V/2.0 A output and 20% ripple, the max allowed output capacitors is 90 mF.
Input Capacitor Selection
The input capacitor can be calculated by Equation 6.
C in(min) + I out(max) @ D max @ 1 f @ V in(ripple)
(eq. 6)
Where Vin(ripple) is the required input ripple voltage.
D max + V out V in(min) is the maximum duty cycle.
(eq. 7)
Power Dissipation
The output capacitor acts to smooth the dc output voltage and also provides energy storage. So the major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is related to capacitance and the ESR. The minimum capacitance required for a certain output ripple can be calculated by Equation 4.
The NCP1597B is available in a thermally enhanced 6-pin, DFN package that dissipates up to 1.0 W at TA = +70C. When the die temperature reaches +165C, the NCP1597B shuts down (see the Thermal-Overload Protection section). The power dissipated in the device is the sum of the power dissipated from supply current (PQ), power dissipated due to switching the internal power MOSFET (PSW), and the power dissipated due to the RMS current through the internal power MOSFET (PON). The total power dissipated in the package must be limited so the junction temperature does not exceed its absolute maximum rating of +150C at maximum ambient temperature.
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NCP1597B
Calculate the power lost in the NCP1597B using the following equations: 1. High side MOSFET The conduction loss in the top switch is:
P HSON + I
2 RMS_HSFET
T J + T C ) P TOTAL @ q JC
(eq. 15)
R DS(on)HS
(eq. 8)
Where:
I RMS_FET + I out 2 ) DI PP 12
2
D
(eq. 9)
qJC is the junction-to-case thermal resistance equal to 1.7C/W. TC is the temperature of the case and TJ is the junction temperature, or die temperature. The case-to-ambient thermal resistance is dependent on how well heat can be transferred from the PC board to the air. Solder the underside-exposed pad to a large copper GND plane. If the die temperature reaches +160C the NCP1597B shut down and does not restart again until the die temperature cools by 40C.
Layout Consideration
DIPP is the peak-to-peak inductor current ripple. The power lost due to switching the internal power high side MOSFET is:
P HSSW + V in @ I out @ t r ) t f @ f SW 2
(eq. 10)
tr and tf are the rise and fall times of the internal power MOSFET measured at SW node. 2. Low side MOSFET The power dissipated in the top switch is:
P LSON + I RMS_LSFET 2 @ R DS(on)LS
(eq. 11)
Where:
I RMS_LSFET + I out 2 ) DI PP 12
2
@ (1 * D )
(eq. 12)
DIPP is the peak-to-peak inductor current ripple. The switching loss for the low side MOSFET can be ignored. The power lost due to the quiescent current (IQ) of the device is:
P Q + V in @ I Q P TOTAL + P HSON ) P HSSW ) P LSON ) P Q
(eq. 13)
IQ is the switching quiescent current of the NCP1597B.
(eq. 14)
Calculate the temperature rise of the die using the following equation:
As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For 1.0MHz switching frequency, switch rise and fall times are typically in few nanosecond range. To prevent noise both radiated and conducted the high speed switching current path must be kept as short as possible. Shortening the current path will also reduce the parasitic trace inductance of approximately 25 nH/inch. At switch off, this parasitic inductance produces a flyback spike across the NCP1597B switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the NCP1597B that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The FB component should be kept as far away as possible from the switch node. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. Board layout also has a significant effect on thermal resistance. Reducing the thermal resistance from ground pin and exposed pad onto the board will reduce die temperature and increase the power capability of the NCP1597B. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple thermal vias under and around this pad to an internal ground plane will also help. Similar treatment to the inductor pads will reduce any additional heating effects.
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NCP1597B
PACKAGE DIMENSIONS
DFN10 3x3, 0.5P CASE 485C-01 ISSUE B
D A B L1
EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03
PIN 1 REFERENCE 2X 2X
0.15 C
0.15 C
0.10 C
10X
DETAIL B
(A3) A A1
SEATING PLANE
0.08 C SIDE VIEW D2
10X
A1
DETAIL A 5
C
L
e
1
10X
K
E2
10 10X
6
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EEE EEE EEE
DETAIL B Side View (Optional) 2.1746
10X
CCC CCC CCC CCC
E
DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD
TOP VIEW
A3
SOLDERING FOOTPRINT*
2.6016
1.8508
3.3048
0.5651
0.3008
10X
0.5000 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NCP1597B/D

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